Thermal stability analysis and performance exploration of asymmetrical dual-k underlap spacer (ADKUS) SOI FinFET for high performance circuit applications
This paper explores the performance of asymmetrical dual-k underlap spacer (ADKUS) SOI FinFET (device-D1) over the wide temperature range (200 K-450 K). An attempt has been made to find out the zero temperature coefficient (ZTC) biased point to enhance the digital, analog and RF performance at 20 nm channel length. The proposed device will be suitable for VLSI circuit’s design, internet of things (IoT) interfacing components and algorithm development for security applications of information technology. The potential parameters of device-D1 like intrinsic gain (AV ), output conductance (gd ), transconductance (gm ), early voltage (VEA ), off current (Ioff) , on current (Ion), Ion/Ioff ratio, gate to source capacitance (Cgs), gate to drain capacitance (Cgd), cut-off frequency (fT), energy (CV2), intrinsic delay (CV/I), energy-delay product (EDP), power dissipation (PD), sub-threshold slope (SS), Q-Factor (gm,max/SS), threshold voltage (Vth) and maximum trans-conductance (gm,max) are subjected to analyze for evaluating the performance of ADKUS SOI FinFET for wide temperature environment. The validation of a temperature based performance of ADKUS SOI FinFET gives an opportunity to design the numerous analog and digital components of internet security infrastructure at wide temperature environment. These ADKUS SOI FinFET based components give new technology to the IoT which has the ability to connect the real world with the digital world and enables the people and machines to know the status of thousands of components simultaneously.
ADKUS SOI FinFET; CMOS; Transconductance; Analog/RF performance; Intrinsic gain; Temperature ;Capacitance
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