Realization of Square-Root Domain integrators with large time-constant
A technique for performing capacitor scaling in Square-Root Domain (SRD) filters is introduced in this paper. This has been achieved through an appropriate modification of the bias in the corresponding SRD integrator blocks. The validity of the proposed scheme has been verified through simulation results, where the most important performance factors have been compared with those obtained through the conventional SRD integrator scheme.
Analog integrated circuits; Low-voltage analog circuits; Companding filters; Capacitor multipliers
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