Design of a Low Offset, Low Noise Amplifier for Neural Recording Applications

Abstract

The design of a capacitive feedback based neural recording amplifier is presented. The prime design requirements in case of neural amplifiers includes low noise, high gain, high CMRR, low power, low area and low offset voltage. However, there is an inherent trade-off between noise-power and area-offset in the design process which needs to be addressed. A Recycling Folded Cascode based Operational Transconductance Amplifier (RFC-OTA) topology is employed to realize the amplifier as it offers better gain and offset voltage as compared to other topologies. The sizing of the transistors has been done with the primary objective of low random offset voltage while meeting other design criteria within the specified range subject to all inherent trade-offs. Simulations have been done in Cadence Virtuoso using SCL 180 nm technology and comparative analysis with other reported designs reveals that the proposed RFC-OTA based neural amplifier design achieves a low random offset voltage of 1.4 mV with a low input noise of 1.38 µV as compared to most of the reported design.